1. Field of the Invention
The invention relates to a three-dimensional integrated circuit. Particularly, the invention relates to a three-dimensional integrated circuit capable of measuring a stacking error.
2. Description of Related Art
Three-dimensional (3D) integrated circuits play an important role in effective use of an integrated circuit space in semiconductor applications, and devices fabricated by the integrated circuits may have different sizes due to different uses of the integrated circuit space. In development of the 3D integrated circuits, whether the integrated circuits on different wafers are accurately combined in the 3D space may influence functions and performance of the 3D integrated circuits.
A general technique for measuring whether the 3D integrated circuit is accurately stacked is to carve two paths having a certain resistance on a contact surface of the wafers, and use a through via technique to conduct measuring contacts on the paths to the wafer surface. When the measuring contacts of the two paths are measured to obtain the same resistance, it represents that the 3D integrated circuit is accurately stacked. Conversely, when the measuring contacts of the two paths are measured to obtain different resistances, it represents that the 3D integrated circuit is not accurately stacked, and a displacement error exists between the wafers. However, according to the conventional measuring method, a displacement amount and a displacement direction cannot be measured, so that is impossible to perform a correction in allusion to the displacement amount.